Semnan University PressJournal of Modeling and Simulation in Electrical and Electronics Engineering2821-07866220260601Multi-Stage Active Networks and Switched-Capacitor Synergy: A Novel Ultra-High-Gain DC-DC Converter for EV Powertrains1201049710.22075/mseee.2026.39908.1239ENHosseinSiavashiDepartment of Electrical Engineering, Hamedan University of Technology, Hamedan, IranPezhmanBayatDepartment of Electrical Engineering, Hamedan University of Technology, Hamedan, IranSeyed MohammadAzimiDepartment of Electrical Engineering, Hamedan University of Technology, Hamedan, IranPeymanBayatDepartment of Electrical Engineering, Hamedan University of Technology, Hamedan, IranJournal Article20251203This paper introduces a novel ultra-high-gain DC–DC converter architecture specifically designed for electric vehicle (EV) applications. The converter integrates a switched-capacitor cell with multi-stage inductor–capacitor–two diodes (LC2D) active networks to achieve sequential energy transfer and voltage stacking while maintaining a minimal component count, including only one semiconductor switch. The proposed topology directly addresses the limitations of conventional converters, namely, restricted voltage gains and excessive voltage stress. Simulation results confirm that the converter achieves a voltage gain of up to 10× at a duty cycle of 41.5%, stepping a 45V battery input to a 450V DC bus level typical of EV traction inverters and onboard chargers. The design consistently delivers conversion efficiencies above 95% across a 2-5kW load range, with stable operation, minimal output ripple, and reduced electromagnetic interference. The supported power range aligns with the needs of auxiliary and small-scale EV subsystems. By combining structural simplicity with quantitative performance improvements, the proposed converter offers a compact, reliable, and cost-effective solution for EV powertrains. Overall, the results demonstrate that the converter provides a rigorously validated pathway toward high-gain, high-efficiency DC–DC conversion in EV systems.https://mseee.semnan.ac.ir/article_10497_930201bcab998c3f64a88cb6b70d2cd6.pdfSemnan University PressJournal of Modeling and Simulation in Electrical and Electronics Engineering2821-07866220260601Impact of Oxide Thickness on the Electrical and Analog/RF Performance of Strained Heterojunction Gate-All-Around Nanosheet FETs21311052810.22075/mseee.2026.40048.1242ENRezaAbbasnezhadDepartment of Electrical Engineering, Shabestar Branch, Islamic Azad University, Shabestar, Iran.Journal Article20251213In this paper, the quantitative assessment of Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET) performance was evaluated for different oxide thicknesses ). The effect of electrostatic control on DC and designing analog circuits, such as transconductance generation factor (TGF), Early voltage ( ), output conductance ( ), transconductance ( ), cut off frequency have been investigated for all devices. Higher TGF and was achieved with for all devices. In the proposed Heterojunction GAA NS FET, we have used Germanium for the source region, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon as the drain region. Incorporating strain in nanosheet and heterojunction structure devices can significantly improve device performance. Before using a model to analyz a semiconductor device, the model parameters must be accurately determined and elaborated. In this case, the Density Gradient (DG) equation, for a given electron Fermi-level distribution, has been solved self-consistently for the electrostatic potential, the Shockley-Read-Hall (SRH) equation for estimating carrier generation, bandgap narrowing for transport behavior and auger recombination. The general results show an improvement of approximately 10% in drain current, transconductance, and unity-gain frequency, providing superior RF performance of the heterojunction structure compared to the conventional GAA NS FET.https://mseee.semnan.ac.ir/article_10528_219800b964a63cb41996e44b4eb10cd6.pdfSemnan University PressJournal of Modeling and Simulation in Electrical and Electronics Engineering2821-07866220260601A Novel 70 GHz Circularly Polarized Fully-Planar Leaky-Wave Antenna with X-shaped Slots for Millimeter-Wave Radar Applications33411054410.22075/mseee.2026.40021.1241ENYaldaTorabiElectrical Engineering Department, University of Zanjan, Zanjan, Iran.Journal Article20251211This paper presents a novel, fully planar circularly polarized periodic leaky-wave antenna (CP-PLWA) designed for wide-beam scanning in the 70 GHz band for millimeter-wave radar applications. A complementary split ring resonator half-mode substrate integrated waveguide (CSRR-HMSIW) feed structure is employed, offering a low-loss, and readily manufacturable implementation. The key innovation is the integration of cascaded X-shaped slots within the radiating patch, which facilitates controlled surface current perturbation and optimized excitation of orthogonal E-field components, resulting in a significantly enhanced circular polarization bandwidth. This design enables backward-to-forward beam scanning while maintaining a fully planar, via-free architecture. Simulated results demonstrate a 20.1% impedance bandwidth (64.4–77.75 GHz), an axial ratio bandwidth exceeding 13.6% (66–75 GHz, AR < 3 dB), and a wide scan angle from –15° to +60°. A gain exceeding 13 dBi (peaking at 16 dBi) is achieved with a simulated radiation efficiency greater than 97%. This compact, fully planar design, fabricated on a Rogers RT/duroid 5880 substrate, advances the state-of-the-art in CP LWAs for 70 GHz millimeter-wave radar systems by simultaneously addressing critical limitations of prior art: achieving wide CP bandwidth in a planar configuration, eliminating fabrication-via complexity, and maintaining high efficiency across a wide scanning range. The proposed antenna offers a promising solution for future high-performance radar applications requiring compact, wideband, and frequency-scanned circularly polarized radiation.https://mseee.semnan.ac.ir/article_10544_893b01d01ddd173d915eeb48ffe68567.pdfSemnan University PressJournal of Modeling and Simulation in Electrical and Electronics Engineering2821-07866220260601Intelligent Fault Tolerant Procedure Design for Nonlinear Dynamics of Induction Furnace Systems: Adaptive Inverse Dynamics Approach43531057810.22075/mseee.2026.39990.1240ENRezaGhasemiDepartment of Electrical Engineering, University of Qom, Qom, Iran.AlirezaBorjaliDepartment of Electrical Engineering, University of Qom, Qom, Iran.Journal Article20251208This paper presents an adaptive inverse dynamic control (AIDC) designed as a fault-tolerant controller for nonlinear models of coreless induction furnace systems. Unlike other research focused on intelligent identification of nonlinear systems, this methodology developed an inverse intelligent process as a universal controller applicable to various nonlinear systems. In induction furnace operations, accurately tracking the target reference temperature is critical for maintaining the crystalline properties of metals; for instance, to produce iron ferrite with 12.22 wt% carbon, the temperature must be held at 912°C. The proposed AIDC approach features an online inverse model identifier, updated using the back-propagation (BP) algorithm. This involves three techniques: 1) multilayer perceptron (MLP), 2) adaptive neuro-fuzzy inference system (ANFIS), and 3) neural networks, all used to identify the system's inverse dynamics as a nonlinear controller. Key benefits of the AIDC include the convergence of faulty states to nominal conditions, robust system design, and reduced impact of faults on system performance. Simulation results demonstrate the effectiveness of this approach.https://mseee.semnan.ac.ir/article_10578_8069e04324fff4058b748655c36129c7.pdfSemnan University PressJournal of Modeling and Simulation in Electrical and Electronics Engineering2821-07866220260601Modeling of the LDMOSFET Transistor with P-Type Windows Based on the BSIM6 Model55601059710.22075/mseee.2026.40209.1245ENAliShokouhi ShoormastiElectrical and Computer Engineering Department, Semnan University, Semnan, IranAbdollahAbbasiElectrical and Computer Engineering Department, Semnan University, Semnan, Iran.Ali AsgharOroujiElectrical and Computer Engineering Department, Semnan University, Semnan, IranJournal Article20251230A physics-based circuit model is presented for a P+ window lateral double-diffused MOSFET (PW-LDMOSFET) structure intended for high-voltage circuit applications. The device employs p-type windows underneath the drift region to reshape the electric field to improve the breakdown voltage. In the proposed model, the PW-LDMOSFET structure is partitioned into two main parts: First, an intrinsic MOSFET modeled by the BSIM6 compact model and second, a voltage-controlled resistor network that represents the segmented drift region. The drift region is divided into six regions, and closed-form analytical expressions are derived for each segment, explicitly accounting for the influence of the depletion effect of P-N junctions on the effective conduction thickness. To verify the proposed model, the PW-LDMOSFET structure is simulated and analyzed using the SILVACO-ATLAS two-dimensional device simulator, including several physical models, and the results are then compared with the proposed model implemented in SILVACO-SmartSpice. Comparisons between the results demonstrate accurate prediction of the drain current characteristics and the dependence of on-resistance on gate voltage and doping concentration of the drift region for gate biases above threshold. Due to the modular formulation of the proposed model, it can be extended to other LDMOSFET structures that use p-type windows.https://mseee.semnan.ac.ir/article_10597_61e6e46e54d87abbbe49fd549c5f9aa3.pdf