In this article, a dynamic circuit technique is suggested to lower the consumed power of wide gates without speed degradation. In the proposed circuit, the voltage swing on the evaluation network is reduced to decrease the consumed power of wide gates. To reduce the consumed power and delay of the suggested circuit, the structure of the output inverter is modified by utilizing the voltage of the footer node of the evaluation network. A current mirror is employed to decrease the contention between the evaluation network and keeper transistors, replicating the evaluation network's leakage current. In addition, the subthreshold leakage current is reduced due to the stacking effect. As a result, the leakage power is lowered and the noise immunity is improved. Wide OR gates are simulated using HSPICE in a 90nm CMOS technology. Simulation results of wide OR gates demonstrate 51% power reduction and 1.82× noise immunity improvement at the same delay as the conventional dynamic circuit for 32-input OR gates. Moreover, a 128-input multiplexer is designed by employing the suggested dynamic circuit. The results demonstrate 13% power reduction and 33% speed improvement for the suggested 128-input multiplexer compared to the conventional multiplexer at the same robustness.
Kumar, R.K. Nagaria, Reduction of variation and leakage in wide fan-in OR logic domino gate. Integration, the VLSI Journal 89 (2023) 229-240.
Asyaei, Energy-Efficient Dynamic Circuit for High Fan-In OR Gates, Journal of Modeling & Simulation in Electrical & Electronics Engineering (MSEEE), 3 (2023) 35-40.
M. Rabaey, A.P. Chandrakasan, B. Nikolic, Digital integrated circuits, 2nd ed., Upper Saddle River, NJ: Prentice Hall, Englewood Cliffs, 2003.
Gronowski, Issues in dynamic logic design, in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, Ch. 8, 2001, pp. 140–157.
Alvandpour, R. Krishnamurthy, K. Sourrty and S. Y. Borkar, A sub-130-nm conditional-keeper technique, IEEE Journal of Solid-State Circuits, 37 (2002) 633-638.
H. Anis, M. W. Allam, and M. I. Elmasry, Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10 (2002) 71-78.
Mahmoodi-Meimand and K. Roy, Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style, IEEE Transactions on Circuits and Systems, 51 (2004) 495-503.
Lih, N. Tzartzanis, W.W. Walker, A leakage current replica keeper for dynamic circuits, IEEE Journal of Solid-State Circuits 42 (2007) 48–55.
Peiravi and M. Asyaei, Current-comparison-based domino: a new low-leakage high speed domino circuit for wide fan-in gates, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21 (2013) 934-943
Asyaei and F. Moradi, A domino circuit technique for noise-immune high fan-in gates, Journal of Circuits, Systems, and Computers, 27 (2018) 1850151:1-23.
Kannan, R. Rangarajan, Low power noise immune node voltage comparison keeper design for high speed architectures. Microprocessors and Microsystems. 77 (2020) 103192.
A. Angeline, VSK. Bhaaskaran, Speed enhancement techniques for clock-delayed dual keeper domino logic style. International Journal of Electronics. 107 (2020)1239-1253.
Kumar, N. Garg, R.K. Nagaria, A Low Power Noise Tolerant Wide Fan-In OR logic Domino Gate, Integration, the VLSI Journal, 104 (2025) 102468.
Asyaei, and E. Ebrahimi, Low power dynamic circuit for power efficient bit lines, AEU-International Journal of Electronics and Communications, 83 (2018) 204-212.
Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht, and A. Fish, Digital subthreshold logic design–motivation and challenges, IEEE 25th Convention of Electrical and Electronics Engineers, (2008) 702-706.
Alioto, G. Palumbo, M. Pennisi, Understanding the effect of process variations on the delay of static and domino logic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18 (2010) 697-710.
Wang, W. Wu, N. Gong, and L. Hou, Domino gate with modified voltage keeper, Paper presented at the ISQED, (2010) 443-446.
Wang and N. R. Shanbhag, An energy-efficient noise-tolerant dynamic circuit technique, IEEE Transactions on Circuits and Systems, 47 (2000) 1300-1306.
Asyaei, A New Circuit Scheme for Wide Dynamic Circuits, Inter. Journal of Engineering Transactions B: Applications, 31 ( 2018) 699-704.
Predictive Technology Model (PTM). 16 nm High-performance V2.1 technology of PTM model. (2022), http://ptm.asu.edu/modelcard/HP/45nm_HP.pm.
Asyaei, M. (2025). A Power-Efficient Noise-Tolerant Circuit Technique for Wide Dynamic Gates. Modeling and Simulation in Electrical and Electronics Engineering, 5(2), 29-36. doi: 10.22075/mseee.2025.38160.1221
MLA
Asyaei, M. . "A Power-Efficient Noise-Tolerant Circuit Technique for Wide Dynamic Gates", Modeling and Simulation in Electrical and Electronics Engineering, 5, 2, 2025, 29-36. doi: 10.22075/mseee.2025.38160.1221
HARVARD
Asyaei, M. (2025). 'A Power-Efficient Noise-Tolerant Circuit Technique for Wide Dynamic Gates', Modeling and Simulation in Electrical and Electronics Engineering, 5(2), pp. 29-36. doi: 10.22075/mseee.2025.38160.1221
CHICAGO
M. Asyaei, "A Power-Efficient Noise-Tolerant Circuit Technique for Wide Dynamic Gates," Modeling and Simulation in Electrical and Electronics Engineering, 5 2 (2025): 29-36, doi: 10.22075/mseee.2025.38160.1221
VANCOUVER
Asyaei, M. A Power-Efficient Noise-Tolerant Circuit Technique for Wide Dynamic Gates. Modeling and Simulation in Electrical and Electronics Engineering, 2025; 5(2): 29-36. doi: 10.22075/mseee.2025.38160.1221
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