Impact of Oxide Thickness on the Electrical and Analog/RF Performance of Strained Heterojunction Gate-All-Around Nanosheet FETs

Document Type : Research Article

Author

Department of Electrical Engineering, Shabestar Branch, Islamic Azad University, Shabestar, Iran.

10.22075/mseee.2026.40048.1242

Abstract

In this paper, the quantitative assessment of Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET) performance was evaluated for different oxide thicknesses ). The effect of electrostatic control on DC and designing analog circuits, such as transconductance generation factor (TGF), Early voltage ( ), output conductance ( ), transconductance ( ), cut off frequency have been investigated for all devices. Higher TGF and  was achieved with  for all devices. In the proposed Heterojunction GAA NS FET, we have used Germanium for the source region, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon as the drain region. Incorporating strain in nanosheet and heterojunction structure devices can significantly improve device performance. Before using a model to analyz a semiconductor device, the model parameters must be accurately determined and elaborated. In this case, the Density Gradient (DG) equation, for a given electron Fermi-level distribution, has been solved self-consistently for the electrostatic potential, the Shockley-Read-Hall (SRH) equation for estimating carrier generation, bandgap narrowing for transport behavior and auger recombination. The general results show an improvement of approximately 10% in drain current, transconductance, and unity-gain frequency, providing superior RF performance of the heterojunction structure compared to the conventional GAA NS FET.

Keywords

Main Subjects

References

[1]    Han MH, Chang ChY, Chen HB, Cheng YCh, Wu YCh. Device and Circuit Performance Estimation of Junctionless Bulk FinFETs, IEEE Transactions on Electron Devices. 60(6) (2013) 1807-1813.
[2]    Vadizadeh M, Darvish G, Fathipour M. A Novel Field Effect Diode (Fed) Structure For Improvement Of Ion/Ioff Ratio Parameter In The Nanometer Regime. IOSR Journal of Electrical and Electronics Engineering. 10. (2015).18-22.
[3]    Es-Sakhi A, Chowdhury M. Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. Microelectronics Journal. 62 (2017). 30-37.
[4]     Liu X, Wu M, Jin X, Chuai R, J Lee. Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures. Journal of Computational Electronics. 13(2) (2014) 509–514.
[5]    Vimala P, Balamurugan NB. Quantum mechanical compact modeling of symmetric double-gate MOSFETs using variational approach. March 2012. Journal of Semiconductors 33(3).
[6]    Rawat AS, Gupta SK. Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications. Microelectronics Journal 66 (2017) 89–102.
[7]    Mil'shtein S, Liessner C. High speed switch using pairs of pHEMTs with shifted gates. Microelectronics Journal 36 (2005) 316–318.
[8]    Abhinav, Rai S. Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications. Microelectronics Journal 64 (2017) 60–68.
[9]    Vaddi R, Agarwal RP, Dasgupta S. Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 10, OCTOBER 2012.
[10]    A. Motamedi, A. A. Orouji, and D. Madadi, “Physical analysis of β-Ga₂O₃ gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence,” J. Comput. Electron., vol. 21, pp. 197–205.
[11]    Te-Kuang CH. A Novel Quasi-3-D Interface Trapped-Charge- Induced Threshold Voltage Model for Quadruple- Gate MOSFETs, Including Equivalent Number of Gates. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 5, MAY 2014.
[12]    Razavi P, Orouji AA. Dual Material Gate Oxide Stack Symmetric Double Gate MOSFET: Improving Short Channel Effects of Nanoscale Double Gate MOSFET. 2008 International Biennial Baltic Electronics Conference (BEC2008), Tallinn.
[13]    Veloso A, Eneman G, De Keersgieter A, Jang D, Mertens H, Matagne P, Dentoni Litta E, Ryckaert J, Horiguchi N. Nanosheet FETs and their Potential for Enabling Continued Moore’s Law Scaling. 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). 978-1-7281-8176-9/21/$31.00.
[14]    Darbandya G, Mothesb S, Schröterb M, Kloesa A, Clausd M. Performance analysis of parallel array of nanowires and a nanosheet in SG, DG and GAA FETs. Solid State Electronics 162 (2019) 107641.
[15]    Tajarrod MH, Rasooli Saghai H. High Ion/Ioff current ratio graphene field effect transistor: the role of line defect. Beilstein J. Nanotechnol. 2015, 6, 2062–2068.
[16]    Mohapatra1 E, Dash TP, Jena J, Das S, Maiti CK. Strain induced Variability Study in Gate-All-Around VerticallyStacked Horizontal Nanosheet Transistors. Physica Scripta, 95(6), 065808 - April 2020.
[17]    J.-W. Han et al. Total ionizing dose effect on nanosheet and nanowire field effect transistor. Microelectronics Reliability 121 (2021) 114145.
[18]    Choi Y, Lee K, Kim KY, Kim S, Lee J, Lee R, Kim HM, Song YS, Kim S, Lee JH, Park BG. Simulation of the Effect of Parasitic Channel Height on Characteristics of Stacked Gate-All-Around Nanosheet FET. Solid-State Electronics (2019). S0038-1101(19)30463.
[19]    LIN et al. Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors. Digital Object Identifier 10.1109/JEDS.2018.2873008.
[20]    Hong-Hyun Park et al. NEGF simulations of stacked silicon nanosheet FETs for performance optimization. 978-1-7281-0940-4/19/$31.00.
[21]    Sakkaki B, Rasooli Saghai H, Darvish G, Khatir M. A new photodetector structure based on graphene nanomeshes: an ab initio study. Beilstein J. Nanotechnol. 2020, 11, 1036–1044.
[22]    Sarkhoush M, Rasooli Saghai H, Soof H. Design and simulation of type I graphene/Si quantum dot superlattice for intermediate band solar cell applications. Frontiers of Optoelectronics (2022)
[23]    Reboh S, Coquand R, Loubet N, Bernier N, Augendre E, Chao R, Li J, Zhang J, Muthinti R, Boureau V, Yamashita T, Faynot O. Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transitors. 2019 IEEE International Electron Devices Meeting (IEDM). 978-1-7281-4032-2/19/$31.00.
[24]    Hong KH, Kim J, Lee SH, Shin J K. Strain-Driven Electronic Band Structure Modulation of Si Nanowires. NANO LETTERS 2008 Vol. 8, No. 5 1335-1340.
[25]    Sun Y, Thompson SE, Nishida T. Strain and Semiconductor Crystal Symmetry. Strain Effect in Semiconductors Theory and Device Applications. Springer Science+Business Media, LLC 2010; 353.
[26]    Usha C, Vimala  P. Analytical Drain Current Modeling and Simulation of Triple Material Gate-All-Around Heterojunction TFETs Considering Depletion Regions. SEMICONDUCTORS Vol. 54 No. 12 2020.
[27]    Jain G et al. Performance analysis of vertically stacked nanosheet tunnel field effect transistor with ideal subthreshold swing.
[28]    Mukesh S, Zhang J. A Review of the Gate-All-Around Nanosheet FET Process Opportunities. Electronics 2022, 11, 3589.
[29]    C Li et al A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application.
[30]    Zhang et al. Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices. Nanomaterials 2021, 11, 646.
[31]    Y. Sun, X. Li, Z. Liu, Y. Liu, X. Li, and Y. Shi, “Vertically stacked nanosheets tree-type reconfigurable transistor with improved ON-current,” IEEE Trans. Electron Devices, vol. 69, no. 1, pp. 370–374, Jan. 2022.
[32]    Hosseini R, Teimourzadeh N, Fathipour M. A new source heterojunction strained channel structure for ballistic gate all around nanowire transistor. J Comput Electron (2014) 13:170–179.
[33]    Zhang Q et al. Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices. Nanomaterials 2021, 11, 646.
[34]    Abbasnezhad R et al. Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors. Journal of Electrical Engineering, vol. 74, no. 6, Slovak University of Technology, 2023, pp. 503-512. https://doi.org/10.2478/jee-2023-0058
[35]    Chang, Sh.T. Nanoscale strained Si/SiGe heterojunction trigate field effect transistors. Jpn. J. Appl. Phys. 44, 5304 (2005).
[36]    Brown AR, Martinez A, Seoane N, Asenovl A. Comparison of Density Gradient and NEGF for 3D Simulation of a Nanowire MOSFET. Proceedings of the 2009 Spanish Conference on Electron Devices. Santiago de Compostela, Spain.
[37]    Ancona MG. Density-gradient theory: a macroscopic approach to quantum confinement and tunneling in semiconductor devices. J Comput Electron (2011) 10:65–97
[38]    Ancona MG. Density-gradient theory: a macroscopic approach to quantum confinement and tunneling in semiconductor devices. J Comput Electron (2011) 10:65–97
[39]    Andrei P. Calibration of the Density-Gradient model by using the multidimensional effective-mass Schr¨odinger equation. J Comput Electron (2006) 5:315–318
[40]    Wettstein A, Schenk, Fichtner W. Quantum Device-Simulation with the Density Gradient Model on Unstructured Grids, IEEE Transactions on Electron Devices. 2001;48:279-283.
[41]    Teng ZM, Ye H, Qinyi T. Generalized Scharfetter-Gummel scheme reducing the crosswind effect for the current continuity equation including energy balance. Computer Physics Communications 79 (1994) 190-200.
[42]    Atlas User Manual, Device Simulation Software; 2011
[43]    D. Madadi and A. A. Orouji, “Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements,” Eur. Phys. J. Plus, vol. 136, p. 785, 2021, doi: 10.1140/epjp/s13360-021-01787-0.
[44]    Richter A, Glunz S W, Werner F, Schmidt J, Cuevas A. Improved quantitative description of Auger Recombination in crystalline silicon. Physical Review B. 86 (2012) 165202.
[45]    R. Abbasnezhad, H. Rasooli Saghai, R. Hosseini, A. Sedghi, and A. Vahedi, “Design and performance analysis of heterojunction dual wire gate-all-around nanosheet field-effect transistor,” Iranian Journal of Physics Research, vol. 24, no. 3, pp. 135–145, 2024, doi: 10.47176/ijpr.24.3.31862
[46]    Valsa et al. An intensive study of three-shaped JL-NSFET: digital and analog/RF perspective. IEEE Transactions on Electronic Devices, VOL. 69, NO. 12, DECEMBER 2022.
[47]    Abbasnezhad R et al. Design and performance analysis of heterojunction dual wire gate all around nanosheet field effect transistor. Journal of Electrical Engineering, Iranian Journal of Physics Research, Vol. 24, No. 3, 2024 DOI: 10.47176/ijpr.24.3.31862.
Journal of Modeling and Simulation in Electrical and Electronics Engineering
Volume 6, Issue 2 - Serial Number 24
In Progress
June 2026
Pages 21-31

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History

  • Receive Date: 13 December 2025
  • Accept Date: 22 February 2026

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