Low-Power FPGA-Based Quantized Neural Network Accelerator for Real-Time Arrhythmia Detection from Single-Lead ECG

Rahmani, Amir Hossein

doi:10.22075/mseee.2026.40918.1267

Low-Power FPGA-Based Quantized Neural Network Accelerator for Real-Time Arrhythmia Detection from Single-Lead ECG

Document Type : Research Article

Author

Amir Hossein Rahmani

Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran.

10.22075/mseee.2026.40918.1267

Abstract

Arrhythmia detection from long-term electrocardiogram (ECG) recordings is essential for early diagnosis of cardiovascular diseases in portable and wearable monitoring systems. This paper presents a low-power hardware accelerator for real-time beat-level arrhythmia classification using an 8-bit quantized 1D convolutional neural network (QNN) implemented on a Xilinx Artix‑7 FPGA. The network is trained and evaluated on the MIT-BIH Arrhythmia Database under an inter-patient scheme and classifies beats into three clinically relevant categories: normal (N), ventricular ectopic (V), and supraventricular ectopic (S). After quantization-aware training, the 8-bit fixed-point model achieves 98.4% overall accuracy, with 99.1% sensitivity and 98.7% positive predictive value (PPV) for N beats, and 96.6% sensitivity with 95.9% PPV for V beats on the held-out test set. The hardware accelerator exploits parallel multiply–accumulate units, on-chip BRAM reuse, and a streaming dataflow to process each 256-sample beat segment in 8.5 µs at 100 MHz, corresponding to a throughput of approximately 118 k beats/s while consuming 0.92 W power. Compared with a 32-bit floating-point implementation on an ARM Cortex-A9 processor, the proposed design provides about 9.3× speedup and 27× lower energy per beat, making it suitable for wearable and home monitoring systems.

Keywords

ECG

Arrhythmia Detection

Quantized Neural Network

FPGA Accelerator

Low Power Design

Subjects

Biomedical Engineering

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