N+ Pocket Core-Shell Nanotube Tunnel Field-Effect Transistor

Document Type : Research Paper

Authors

1 Electrical engineering department of Amirkabir university, Tehran 1591634311, Iran

2 Department of Electrical and Computer Engineering,Semnan University, Semnan 3513119111, Iran

Abstract

One of the attractive candidates for improving the performance of tunnel transistors is cylindrical structures due to their impressive electrostatic control of the gate. But the on-state current of tunnel transistors is still very low compared to MOSFETs. An alternative is to use core-shell nanotubes rather than nanowires. In this article, we present a core-shell TFET nanotube based on a heterogeneous germanium/silicon structure. In our proposed structure, an N+ pocket is employed to enhance the on-state current. A possible manufacturing method is also proposed that is fully compatible with CMOS  technology. The main parameters of this transistor are 97.85 μA / μm on-state current, Ion / Ioff ratio of 8.26×108, SSavg  mV/dec 21.15, and fT of 878.95 GHz.

Keywords

Main Subjects


[1] N. Z. Haron and S. Hamdioui, "Why is CMOS scaling coming to an END?," in 2008 3rd International Design and Test Workshop, 2008, pp. 98-103: IEEE. DOI: https://doi.org/10.1109/IDT.2008.4802475
[2] J. Knoch and J. Appenzeller, "A novel concept for field-effect transistors-the tunneling carbon nanotube FET," in 63rd Device Research Conference Digest, 2005. DRC'05., 2005, vol. 1, pp. 153-156: IEEE, https://doi.org/10.1109/DRC.2005.1553099
[3] A. C. Seabaugh and Q. Zhang, "Low-voltage tunnel transistors for beyond CMOS logic," Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, 2010.https://doi.org/10.1109/JPROC.2010.2070470
[4] S. Salahuddin and S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices," Nano Letters, vol. 8, no. 2, pp. 405-410, 2008.https://doi.org/10.1021/nl071804g
[5] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "Impact ionization MOS (I-MOS)-Part I: device and circuit simulations," IEEE Transactions on electron devices, vol. 52, no. 1, pp. 69-76, 2004.https://doi.org/10.1109/TED.2004.841344
[6] D. B. Abdi and M. J. Kumar, "Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain," IEEE Journal of the Electron Devices Society, vol. 2, no. 6, pp. 187-190, 2014.https://doi.org/10.1109/JEDS.2014.2327626
[7] U. E. Avci, D. H. Morris, and I. A. Young, "Tunnel field-effect transistors: Prospects and challenges," IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 88-95, 2015.https://doi.org/10.1109/JEDS.2015.2390591
[8] N. Bagga, A. Kumar, and S. Dasgupta, "Demonstration of a novel two source region tunnel FET," IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 5256-5262, 2017.https://doi.org/10.1109/TED.2017.2759898
[9] I. C. Cherik and S. Mohammadi, "Enhanced on-state current and suppressed ambipolarity in germanium-source dual vertical-channel TFET," Semiconductor Science and Technology, 2020.https://doi.org/10.1088/1361-6641/abd63e
[10] I. C. Cherik and S. Mohammadi, "Germanium-source L-shaped TFET with dual-in-line tunneling junction," Applied Physics A, vol. 127, no. 7, pp. 1-8, 2021.https://doi.org/10.1007/s00339-021-04677-5
[11] S. Kim, W. Y. Choi, and B.-G. Park, "Vertical-structured electron-hole bilayer tunnel field-effect transistor for extremely low-power operation with high scalability," IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 2010-2015, 2018.https://doi.org/10.1109/TED.2018.2817569
[12] L. Lattanzio, L. De Michielis, and A. M. Ionescu, "Complementary germanium electron-hole bilayer tunnel FET for sub-0.5-V operation," IEEE Electron Device Letters, vol. 33, no. 2, pp. 167-169, 2011.https://doi.org/10.1109/LED.2011.2175898
[13] H. M. Fahad and M. M. Hussain, "High-performance silicon nanotube tunneling FET for ultralow-power logic applications," IEEE transactions on electron devices, vol. 60, no. 3, pp. 1034-1039, 2013.https://doi.org/10.1109/TED.2013.2243151
[14] G. Musalgaonkar, S. Sahay, R. S. Saxena, and M. J. Kumar, "A line tunneling field-effect transistor based on misaligned core-shell gate architecture in emerging nanotube FETs," IEEE Transactions on Electron Devices, vol. 66, no. 6, pp. 2809-2816, 2019.https://doi.org/10.1109/TED.2019.2910156
[15] N. Kumar, S. I. Amin, and S. Anand, "Design and Performance Optimization of Novel Core-Shell Dopingless GAA-Nanotube TFET With Si 0.5 Ge 0.5-Based Source," IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 789-795, 2020.https://doi.org/10.1109/TED.2020.2965244
[16] A. Hanna and M. M. Hussain, "Si/Ge hetero-structure nanotube tunnel field-effect transistor," Journal of Applied Physics, vol. 117, no. 1, p. 014310, 2015.https://doi.org/10.1063/1.4905423
[17] S. H. Kim, S. Agarwal, Z. A. Jacobson, P. Matheu, C. Hu, and T.-J. K. Liu, "Tunnel field-effect transistor with raised germanium source," IEEE electron device letters, vol. 31, no. 10, pp. 1107-1109, 2010.https://doi.org/10.1109/LED.2010.2061214
[18] Silvaco, ATLAS Device Simulation Software User’s Manual, no. version 3.2. 2015
[19] D. Querlioz, J. Saint-Martin, K. Huet, A. Bournel, V. Aubry-Fortuna, C. Chassat, S. Galdin-Retailleau, and P. Dollfus, "On the ability of the particle Monte Carlo technique to include quantum effects in nano-MOSFET simulation," IEEE transactions on electron devices, vol. 54, no. 9, pp. 2232-2242, 2007.https://doi.org/10.1109/TED.2007.902713
[20] S. Sant, A. Schenk, K. Moselund, and H. Riel, "Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero tunnel FETs," in 2016 74th Annual Device Research Conference (DRC), 2016, pp. 1-2: IEEE. DOI: https://doi.org/10.1109/DRC.2016.7548413.
[21] I. C. Cherik, S. Mohammadi and A. A. Orouji, "Switching Performance Enhancement in Nanotube Double-Gate Tunneling Field-Effect Transistor With Germanium Source Regions," in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 364-369, Jan. 2022, DOI: 10.1109/TED.2021.3124984.
[22] I. C. Cherik and S. Mohammadi, "Vertical Cladding Layer Based Doping-Less Tunneling Field Effect Transistor, a Novel Low-Power High-Performance Device," IEEE Transactions on Electron Devices, 2021.https://doi.org/10.1109/TED.2021.3138669
[23] A. Bhattacharyya, M. Chanda, and D. De, "GaAs0. 5Sb0. 5/In0. 53Ga0. 47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement," Superlattices and Microstructures, vol. 142, p. 106522, 2020.https://doi.org/10.1016/j.spmi.2020.106522
[24] A. Acharya, A. B. Solanki, S. Dasgupta, and B. Anand, "Drain current saturation in line tunneling-based TFETs: An analog design perspective," IEEE Transactions on Electron Devices, vol. 65, no. 1, pp. 322-330, 2017.10.1109/TED.2017.2771249.
[25] M. R. Tripathy, A. K. Singh, K. Baral, P. K. Singh, and S. Jit, "III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications," Superlattices and Microstructures,p.106494,2020.https://doi.org/10.1016/j.spmi.2020.106494.
[26] C. Pandey, A. Singh, and S. Chaudhury, "Effect of asymmetric gate-drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances," Applied Physics A, vol. 126, no. 3, pp. 1-12, 2020.https://doi.org/10.1007/s00339-020-3402-2.