Energy-Efficient Dynamic Circuit for High Fan-In OR Gates

Document Type : Research Paper

Author

School of Engineering, Damghan University, Damghan, Iran.

Abstract

Dynamic circuits offer a promising solution due to their low power consumption and high performance compared to static ones. However, dynamic circuits have their limitations, particularly in terms of robustness. This article presents a new dynamic circuit that reduces power consumption and delays for high-fan-in OR gates without significant loss of robustness.  In the new dynamic circuit, the pull-down network (PDN) is split to increase the speed. Furthermore, employing a reference circuit decreases the conflict current that occurs between the PDN and keeper transistors. For this purpose, the reference circuit replicates the leakage current of the PDN. Therefore, the power and delay of the presented circuit are reduced. In addition, the sub-threshold leakage current and hence the leakage power are decreased in the PDN because of the body effect. The results of simulating high fan-in OR gates in a 90nm CMOS technology show 45% and 53% reduction in delay and power consumption, respectively while maintaining the same level of robustness as the conventional circuit for 64 inputs OR gates. Moreover, the tag comparator designed with the presented circuit shows a 2.65 times improvement in the figure of merit compared to the conventional design.

Keywords

Main Subjects

References

  • Kumar, R.K. Nagaria, “A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates,” Analog Integr. Circuits Signal Process, vol. 102, pp. 9-25, 2020.
  • Kumar and R.K. Nagaria, “Reduction of variation and leakage in wide fan-in OR logic domino gate,” Integration, the VLSI Journal, vol. 89, pp. 229-240, 2023.
  • Mostafa, M. Anis, M. Elmasry, “Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic OR gates,” IEEE Trans. Circ. Syst., vol. 58, pp. 1785-1797, 2011. doi:10.1109/TCSI.2011.2107171
  • Lih, N. Tzartzanis, W.W. Walker, “A leakage current replica keeper for dynamic circuits,” IEEE J. Solid-State Circ, vol. 42, pp. 48-55, 2007. doi:10.1109/JSSC.2006.885051
  • Suzuki, C.H. Kim, K. Roy, “Fast tag comparator using diode partitioned domino for 64-bit microprocessors,” IEEE Trans. Circuits Syst., vol. 54, pp. 322–328, 2007. doi:10.1109/TCSI.2006.885998
  • Angeline and VSK. Bhaaskaran, “Speed enhancement techniques for clock-delayed dual keeper domino logic style,” International Journal of Electronics, vol. 107, pp. 1239-1253, 2020. doi: 10.1080/00207217.2020.1726486
  • Kannan and R. Rangarajan, “Low power noise immune node voltage comparison keeper design for high-speed architecture,” Microprocessors and Microsystems Journal, vol. 77, pp. 103192, 2020. doi:10.1016/j.micpro.2020.103192
  • Asyaei, “New dynamic logic style for energy efficient tag comparators,” Microprocessors and Microsystems Journal, vol. 90, pp. 104522, 2022. doi:10.1016/j.micpro.2022.104522 
  • Asyaei, “New partitioned domino circuit for power-efficient wide gates,” Elsevier Integration, the VLSI Journal, vol. 80, pp. 320-327, 2023. doi:10.1016/j.vlsi.2022.10.010   
  • M. Rabaey, A.P. Chandrakasan, B. Nikolic, “Digital integrated circuits,” 2nd ed., Upper Saddle River, NJ: Prentice hall Englewood Cliffs, 2003.
  • Ding and P. Mazumder, “On circuit techniques to improve noise immunity of CMOS dynamic logic,” IEEE Trans. on Very Large Scale Integ. (VLSI) Syst., vol. 12, pp. 910-925, 2004.
  • HSpice Simulation and Analysis Users Guide, [online] Available: https:// https://www.synopsys.com/.  
  • Alioto, G. Palumbo, M. Pennisi, “Understanding the effect of process variations on the delay of static and domino logic,” IEEE Trans. on Very Large Scale Integ. (VLSI) Syst., vol. 18, pp. 697-710, 2010. doi:10.1109/TVLSI.2009.2015455
  • Asyaei, “A new low-power dynamic circuit for wide fan-in gates,” Integration, the VLSI Journal., vol. 60, pp. 263-271, 2018. doi: 10.1016/j.vlsi.2017.10.010    
  • Kandpal, T. Pokhrel, S. Saini, A. Majumder “A variation resilient keeper design for high-performance domino logic applications,” Integration, the VLSI Journal, vol. 88, pp. 1-9, 2023. doi: 10.1016/j.vlsi.2022.08.007
  M. Asyaei, “A New Circuit Scheme for Wide Dynamic Circuits,” Inter. J. of Engineering Trans. B: Applications, vol. 31, pp. 699-704, 2018. doi: 10.5829/ije.2018.31.04a.03
Modeling and Simulation in Electrical and Electronics Engineering
Volume 3, Issue 3 - Serial Number 13
November 2023
Pages 35-40

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History

  • Receive Date: 10 August 2024
  • Revise Date: 11 October 2024
  • Accept Date: 29 January 2025

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