[1] C. S. Vaucher, Architectures for RF Frequency Synthesizers, vol. 693. Springer, 2006.
[2] R. J. Baker, CMOS: Circuit Design, Layout, and Simulation. Hoboken, NJ, USA: John Wiley & Sons, 2019.
[3] C. Barrett, “Fraction/Integer-N PLL basics,” Texas Instruments, Dallas, TX, USA, 1999.
[4] X. Li, J. Zhang, Y. Zhang, W. Wang, H. Liu, and C. Lu, “A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur,” AEU–International Journal of Electronics and Communications, vol. 85, pp. 23–31, 2018.
[5] D. Banerjee, PLL Performance, Simulation, and Design, 4th ed. 2006.
[6] K. Shu and E. Sánchez-Sinencio, CMOS PLL Synthesizers: Analysis and Design. Boston, MA, USA: Springer, 2005.
[7] X. He, Low Phase Noise CMOS PLL Frequency Synthesizer Analysis and Design. College Park, MD, USA: University of Maryland, 2007.
[8] T. Bourdi and I. Kale, CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation. Dordrecht, The Netherlands: Springer, 2007.
[9] H. N. M. Al-Nuaimi, “Design and simulation fractional-N phase locked loop frequency synthesizer using sigma-delta modulator for Bluetooth systems,” [Publication details not provided].
[10] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters. Hoboken, NJ, USA: John Wiley & Sons, 2017.
[11] A. Hu, D. Liu, and K. Zhang, “Analysis and optimization of seamless switching golden states of multi-modulus divider in software defined Σ-Δ frequency synthesizer,” Microelectronics Journal, vol. 84, pp. 26–35, 2019.
[12] J. Jo, D. Kim, A. Hejazi, Y. Pu, Y. Jung, H. Huh, S. Kim, J.-M. Yoo, and K.-Y. Lee, “Low phase-noise, 2.4 and 5.8 GHz dual-band frequency synthesizer with Class-C VCO and bias-controlled charge pump for RF wireless charging system in 180 nm CMOS process,” Electronics, vol. 11, no. 7, Art. no. 1118, 2022.
[13] S. A. Shehab and A. Z. Yonis, “Design and simulation of fractional-N PLL 2.4 GHz for WLAN in IEEE 802.11 standards,” in Proc. 11th Int. Conf. Wireless Networks and Mobile Communications (WINCOM), 2024, pp. 1–6.
[14] M. K. M. Ali and O. Hashemipour, “Fast locking technique for phase locked loop based on phase error cancellation,” AEU–International Journal of Electronics and Communications, vol. 109, pp. 99–106, 2019.
[15] Y. Wang, Y. Wang, Z. Wu, Z. Quan, and J. J. Liou, “A programmable frequency divider with a full modulus range and 50% output duty cycle,” IEEE Access, vol. 8, pp. 102032–102039, 2020.
[16] S. Kazeminia, “Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements,” AEU–International Journal of Electronics and Communications, vol. 127, Art. no. 153477, 2020.
[17] J. K. Sahani, A. Singh, and A. Agarwal, “A 1 μs locking time dual loop ADPLL with foreground calibration-based 6 ps resolution flash TDC in 180 nm CMOS,” Circuits, Systems, and Signal Processing, vol. 41, no. 3, pp. 1299–1323, 2022.
[18] J. Yin, H. Li, X. Lin, R. P. Martins, and P.-I. Mak, “Progress and trends of low-jitter fractional-N PLL,” Journal of Semiconductors, vol. 46, pp. 1–4, 2025.
[19] T. Li, C. Guo, W. Zhang, J. Huang, J. Zeng, and J.-A. Zhang, “A low power low phase noise wide frequency range PLL,” Microelectronics Journal, vol. 154, Art. no. 106441, 2024.
[20] Y. Li, B. Xun, Y. Shi, X. Xu, M. Li, H. Zhu, and Q. Sun, “A compact, low-power, and low-jitter fractional-N phase-locked loop with a single-ended ring voltage-controlled oscillator in a 12 nm CMOS FinFET,” Electronics, vol. 13, no. 13, Art. no. 2617, 2024.
[21] L. Sun, Y. Luo, Z. Deng, J. Wang, and B. Liu, “Novel power-efficient fast-locking phase-locked loop based on adaptive time-to-digital converter-aided acceleration compensation technology,” Electronics, vol. 13, no. 18, Art. no. 3586, 2024.
[22] F. Herzel, A. Ergintav, and G. Fischer, “A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar,” Integration, vol. 76, pp. 139–147, 2021.
[23] V. Lad, A. Mehendale, and S. S. Narkhede, “A comprehensive survey on phase locked loop IC design,” in Proc. Int. Conf. Information and Communication Technology for Competitive Strategies, Singapore: Springer Nature, 2024, pp. 223–234.
[24] S. Pourakbari, “Design of fractional frequency synthesizer based on sigma delta divider in satellite applications,” New Researches in Electronic Defense Systems, vol. 2, no. 5, pp. 34–39, 2024.
[25] E. Kaur, E. S. Singh, and S. Kaur, “Design and analysis of D flip-flop using different technologies,” International Journal of Innovative Research in Computer and Communication Engineering, vol. 8, 2015.
[26] S. Malipatil, “Design of a low power D-flip flop using AVL technique,” International Journal of Advanced Research in Computer and Communication Engineering, vol. 4, no. 9, pp. 291–293, 2015.
[27] G. Sushma and V. Ramesh, “Low power high speed D flip flop design using improved SVL technique,” in Proc. 2016 Int. Conf. Recent Trends in Information Technology (ICRTIT), 2016, pp. 1–5.
[28] F. Dai, C. Plett, and J. Rogers, Integrated Circuit Design for High-Speed Frequency Synthesis. Boston, MA, USA: Artech House, 2006.
[29] H. B. Kim and Y. S. Kim, “Optimizing CML-CMOS converter through sizing transistors for producing 50% duty square wave,” Journal of Integrated Circuits and Systems, vol. 6, no. 3, 2020.
[30] A. Hu, “Multi-modulus divider in fractional-N frequency synthesizer for direct conversion DVB-H receiver,” M.S. thesis, The Ohio State University, Columbus, OH, USA, 2007.
[31] M. Amiri, “Discrimination of neutron and photon signals,” Ph.D. dissertation, Masaryk University, Brno, Czech Republic, 2012.
[32] B. Holdsworth and C. Woods, Digital Logic Design. Oxford, U.K.: Elsevier, 2002.
[33] A. Gowthami, “MASH 1-2 delta sigma modulator with quantizer for fractional-N frequency synthesizer,” Transfer, vol. 5, no. 3, 2018.
[34] H. R. Erfani-Jazi and N. Ghaderi, “A divider-less, high speed and wide locking range phase locked loop,” AEU–International Journal of Electronics and Communications, vol. 69, no. 4, pp. 722–729, 2015.