An Efficient Approximate Vedic Multiplier Circuit Design by Bit-Slicing Method Based on QCA Technology

Bolokian, Mohammad; Houshmand, Monireh; Danaie, Mohammad; Boloukian, Hossein

doi:10.22075/mseee.2026.40500.1252

An Efficient Approximate Vedic Multiplier Circuit Design by Bit-Slicing Method Based on QCA Technology

Articles in Press

Document Type : Research Article

Authors

Mohammad Bolokian ¹

Monireh Houshmand ²

mohammad danaie ¹

hossein boloukian ³

¹ Department of Electrical Engineering, Semnan University, Semnan, Iran.

² Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran.

³ Department of Electrical Engineering, Pars Razavi University, Gonabad, Iran.

10.22075/mseee.2026.40500.1252

Abstract

Nowadays, due to the ubiquity of portable electronic equipment and their limited battery charge, low-power circuit design based on compression has been one of the biggest criteria for researchers, which will create some limitations and challenges. However, one way to reduce power consumption is to use approximate units based on quantum cellular automata technology in systems. In this study, we design an approximate multiplier using quantum cellular automata technology. Using the full-adder design scheme to obtain partial multiplications and place them in a particular arrangement, we arrive at an approximate multiplier. The proposed design can improve on quantum costs (53%), constant inputs (15%), and Area (55%). In addition, it is shown that the QCA technology is effective for implementing complex computational circuits and can provide a good performance over a precise circuit. The design and the simulation of the circuits in this study have been performed using the QCA Designer tool version 2.0.3.

Keywords

Quantum Dot Cellular Automata

Quantum Computing

Qca Approximate Multiplier

Approximation Calculations

Low-Power Circuit Design

Very Compact Quantum Circuits

Subjects

Electronics

[1] Srivastava, S., Sarkar, S., Bhanja, S. Power dissipation bounds and models for quantum-dot cellular automata circuits. in 2006 Sixth IEEE Conference on Nanotechnology. (2006). IEEE.

[2] Timarchi, S., Fazlali, M. Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n− 1, 2n, 2n+ 1}. IET computers & digital techniques, (2012). 6(5): p. 269-276.

[3] Rahimzadeh, E., Timarchi, Radix-4 implementation of redundant interleaved modular multiplication on FPGA. Iranian Conference on Electrical Engineering (ICEE), (2014).

[4] Fazlali, M., Timarchi, H.V.S and Malazi, H. Fast architecture for decimal digit multiplication. Microprocessors and Microsystems, (2015). 39(4-5): p. 296-301.

[5] Moore, G.E., Cramming more components onto integrated circuits. Proceedings of the IEEE, (1998). 86(1): p. 82-85.

[6] Landauer, R., Irreversibility and heat generation in the computing process. IBM journal of research and development, (1961). 5(3): p. 183-191.

[7] Lent, C.S., et al., Quantum cellular automata. Nanotechnology, (1993). 4(1): p. 49.

[8] Narayanamoorthy, S., et al., Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE transactions on very large scale integration (VLSI) systems, 2(6) 26.014: p. 1180-1184.

[9] Hashemi, S., R.I. Bahar, and S. Reda. DRUM: A dynamic range unbiased multiplier for approximate applications. in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). (2015). IEEE.

[10] Akbari, O., et al., Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (2017). 25(4): p. 1352-1361.

[11] Venkatachalam, S. and S.-B. Ko, Design of power and area efficient approximate multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (2017). 25(5): p. 1782-1786.

[12] Jiang, H., et al., Low-power approximate unsigned multipliers with configurable error recovery. IEEE Transactions on Circuits and Systems I: Regular Papers, (2018). 66(1): p. 189-202.

[13] Du, K., P. Varman, and K. Mohanram. High performance reliable variable latency carry select addition. in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE). (2012). IEEE.

[14] Liu, W., et al., Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications. IEEE Transactions on Circuits and Systems I: Regular Papers, (2018). 65(9): p. 2856-2868.

[15] Zendegani, R., et al., RoBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (2016). 25(2): p. 393-401.

[16] Bahar, A.N. and K.A. Wahid, Design of QCA-serial parallel multiplier (QSPM) with energy dissipation analysis. IEEE transactions on circuits and systems II: express briefs, (2019). 67(10): p. 1939-1943.

[17] Wang, X., Designing digital circuits based on quantum-dots cellular automata using nature-inspired metaheuristic algorithms: A systematic literature review. Optik, (2022): p. 169251.

[18] Zhang, Y., et al., Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates. International Journal of Circuit Theory and Applications, (2016). 44(7): p. 1351-1366.

[19] Biswas, P., N. Gupta, and N. Patidar, Basic reversible logic gates and it’s QCA implementation. Int. Journal of Engineering Research and Applications, (2014). 4(6): p. 12-16.

[20] Moshnyaga, V.G. Design of minimum complexity reversible multiplier. in TENCON 2015-2015 IEEE Region 10 Conference. (2015). IEEE.

[21] Zhou, R.-G., Y.-C. Li, and M.-Q. Zhang, Novel designs for fault tolerant reversible binary coded decimal adders. International Journal of Electronics, (2014). 101(10): p. 1336-1356.

[22] Cho, H. and E.E. Swartzlander, Adder and multiplier design in quantum-dot cellular automata. IEEE Transactions on Computers, (2009). 58(6): p. 721-727.

[23] Immareddy, S. and A. Sundaramoorthy, A survey paper on design and implementation of multipliers for digital system applications. Artificial Intelligence Review, (2022): p. 1-29.

[24] Han, J. and M. Orshansky. Approximate computing: An emerging paradigm for energy-efficient design. in 2013 18th IEEE European Test Symposium (ETS). (2013). IEEE.

[25] Alioto, M., Enabling the Internet of Things: From Integrated Circuits to Integrated Systems. (2017): Springer.

[26] Alioto, M. Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing. in Design, Automation & Test in Europe Conference & Exhibition (DATE), (2017). IEEE.

[27] Alioto, M., V. De, and A. Marongiu, Guest editorial energy-quality scalable circuits and systems for sensing and computing: From approximate to communication-inspired and learning-based. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, (2018). 8(3): p. 361-368.

[28] Shin, D. and S.K. Gupta. Approximate logic synthesis for error tolerant applications. in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). (2010). IEEE.

[29] Frustaci, F., et al., SRAM for error-tolerant applications with dynamic energy-quality management in 28 nm CMOS. IEEE Journal of Solid-state circuits, (2015). 50(5): p. 1310-1323.

[30] Neeharika, R., K.M. Venkanna, and M.M. Kavitha, Design of low-power high-speed truncation-error tolerant adder and its application in digital signal processing. Int Eng Res Appl, (2012). 2(2): p. 939-944.

[31] Gupta, V., et al., Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (2012). 32(1): p. 124-137.

[32] Mahdiani, H.R., et al., Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Transactions on Circuits and Systems I: Regular Papers, (2009). 57(4): p. 850-862.

[33] Almurib, H.A., T.N. Kumar, and F. Lombardi. Inexact designs for approximate low power addition by cell replacement. in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). (2016). IEEE.

[34] Frustaci, F., et al., Approximate SRAMs with dynamic energy-quality management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (2016). 24(6): p. 2128-2141.

[35] Imani, M., D. Peroni, and T. Rosing. CFPU: Configurable floating point multiplier for energy-efficient computing. in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC). (2017). IEEE.

[36] Miao, J., et al. Modeling and synthesis of quality-energy optimal approximate adders. in Proceedings of the International Conference on Computer-Aided Design. (2012).

[37] Frustaci, F., et al., Energy-quality scalable adders based on nonzeroing bit truncation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (2018). 27(4): p. 964-968.

[38] Huang, J. and F. Lombardi, Design and test of digital circuits by quantum-dot cellular automata. (2007): Artech.

[39] Mahmoodi, Y. and M.A. Tehrani. Novel fault tolerant QCA circuits. in 2014 22nd Iranian Conference on Electrical Engineering (ICEE). (2014). IEEE.

[40] Gowthami, P. and R. Satyanarayana, Performance evaluation of reversible Vedic multiplier. ARPN J Eng Appl Sci, (2018). 13(2): p. 1002-1008.

[41] kolahnoori, M. and D. Bahrepour . Approximate design of full adder circuit with low power consumption by bit cutting method based on QCA technology. in 8th National Congress of Electrical and Computer Engineering of Iran. (2022). 42[In persian].