Dual-Channel Indium Nitride Tunnel Field Effect Transistor: A Comprehensive Study on Design, Sensitivity, and Electrical Performance

Document Type : Research Paper


Department of Electronics, Yadegar- e- Imam Khomeini (RAH) Shahr-e-Rey Branch, Islamic Azad University, Tehran, Iran.


This paper presents a vertical tunnel field effect transistor (TFET) that incorporates two parallel side wall channels. The channel material utilized in this design is Indium Nitride (InN), which is sandwiched between lateral gates. This configuration allows for the amplification of drive current through extended tunneling area, taking advantage of the benefits offered by the vertical structure. InN is a promising channel material due to its high electron mobility and high electron velocity, which enhances the device performance. The impact of critical design parameters on the device performance is comprehensively assessed. The optimal values of a 2D variation matrix of threshold voltage and on-state current can be determined by considering the variation of gate workfunction and source doping density, which are two crucial design measures. Additionally, a statistical analysis is carried out to evaluate the sensitivity of the device main electrical parameters with respect to the variation of critical design parameters. The findings indicate that the device attains a current of 1 mA when in the on-state, with an on/off current ratio of 1.3×1010. Additionally, it exhibits an average subthreshold swing of 20 mV/dec, and maximum subthreshold swing of 4.8 mV/dec, leading to reduced power consumption and enhanced switching speeds.


Main Subjects

[1]  Pandey, Nilesh, and Yogesh Singh Chauhan. "Analytical modeling of short-channel effects in MFIS negative-capacitance FET including quantum confinement effects." IEEE Transactions on Electron Devices 67, no. 11 (2020): 4757-4764. https://doi.org/10.1109/TED.2020.3022002.
[2]    Pino-Monroy, Dayana A., Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragan, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, and Sylvain Bourdel. "Design-oriented all-regime all-region 7-parameter short-channel MOSFET model based on inversion charge." IEEE Access 10 (2022): 86270-86285. https://doi.org/10.1109/ACCESS.2022.3198644.
[3]   Karthik, Kadava RN, and Chandan Kumar Pandey. "A review of tunnel field-effect transistors for improved ON-state behaviour." Silicon 15, no. 1 (2023): 1-23. https://doi.org/10.1007/s12633-022-02028-4.
[4]  Joshi, Tripuresh, Yashvir Singh, and Balraj Singh. "Extended-source double-gate tunnel FET with improved DC and analog/RF performance." IEEE Transactions on Electron Devices 67, no. 4 (2020): 1873-1879. https://doi.org/10.1109/TED.2020.2973353.
[5]  Das, Basab, and Brinda Bhowmick. "Effect of curie temperature on ferroelectric tunnel FET and its RF/analog performance." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 68, no. 4 (2020): 1437-1441. https://doi.org/10.1109/TUFFC.2020.3033761.
[6] Talukdar, Jagritee, Gopal Rawat, Kunal Singh, and Kavicharan Mummaneni. "Low frequency noise analysis of single gate extended source tunnel FET." Silicon 13 (2021): 3971-3980. https://doi.org/10.1007/s12633-020-00712-x.
[7]   Convertino, Clarissa, Cezar B. Zota, Heinz Schmid, Daniele Caimi, Lukas Czornomaz, Adrian M. Ionescu, and Kirsten E. Moselund. "A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon." nature electronics 4, no. 2 (2021): 162-170. https://doi.org/10.1038/s41928-020-00531-3.
[8]    Rajan, Chithraja, Dip Prakash Samajdar, and Anil Lodhi. "Investigation of DC, RF and linearity performances of III–V semiconductor-based electrically doped TFET for mixed signal applications." Journal of Electronic Materials 50 (2021): 2348-2355. https://doi.org/10.1007/s11664-021-08753-7.
[9]   Tripathy, Manas Ranjan, Ashish Kumar Singh, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit. "III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications." Superlattices and Microstructures 142 (2020): 106494. https://doi.org/10.1016/j.spmi.2020.106494.
[10] Choi, Yejoo, Yuri Hong, Eunah Ko, and Changhwan Shin. "Optimization of double metal-gate InAs/Si heterojunction nanowire TFET." Semiconductor Science and Technology 35, no. 7 (2020): 075024. https://doi.org/10.1088/1361-6641/ab8b1f.
[11] Singh, Sonal, Mamta Khosla, Girish Wadhwa, and Balwinder Raj. "Design and analysis of double-gate junctionless vertical TFET for gas sensing applications." Applied Physics A 127 (2021): 1-7. https://doi.org/10.1007/s00339-020-04156-3.
[12] Chappa, Vinay K., Ajeet K. Yadav, Anupal Deka, and Robin Khosla. "Investigating the effects of doping gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications." Materials Science and Engineering: B 299 (2024): 116996. https://doi.org/10.1016/j.mseb.2023.116996.
[13] Gupta, Shilpi, Subodh Wairya, and Shailendra Singh. "Analytical modeling and simulation of a triple metal vertical TFET with hetero-junction gate stack." Superlattices and Microstructures 157 (2021): 106992. https://doi.org/10.1016/j.spmi.2021.106992.
[14] Ye, Hao, and Jianping Hu. "A Fully Analytical Current Model of Two-Input TFETs Considering the Channel Coupling Effects." Arabian Journal for Science and Engineering 46, no. 10 (2021): 10033-10042. https://doi.org/10.1007/s13369-021-05815-0.
[15] Manikanta, K., and Umakanta Nanda. "Linearity and RF analysis of double gate reverse T-shaped TFET with L-shaped pocket across the Si-Ge source region." Physica Scripta 98, no. 10 (2023): 105003. https://doi.org/10.1088/1402-4896/acf3b2.
[16] Xie, Haiwu, Hongxia Liu, Tao Han, Wei Li, Shupeng Chen, and Shulong Wang. "TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel." Micro & Nano Letters 15, no. 4 (2020): 272-276. https://doi.org/10.1049/mnl.2019.0398.
[17] Yun, Seunghyun, Jeongmin Oh, Seokjung Kang, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim. "F-shaped tunnel field-effect transistor (tfet) for the low-power application." micromachines 10, no. 11 (2019): 760. https://doi.org/10.3390/mi10110760.
[18] Chen, Shupeng, Shulong Wang, Hongxia Liu, Tao Han, Haiwu Xie, and Chen Chong. "A novel dopingless fin-shaped SiGe channel TFET with improved performance." Nanoscale Research Letters 15 (2020): 1-8. https://doi.org/10.1186/s11671-020-03429-3.
[19] Alper, Cem, Pierpaolo Palestri, Jose Luis Padilla, and Adrian M. Ionescu. "The electron-hole bilayer TFET: Dimensionality effects and optimization." IEEE Transactions on Electron Devices 63, no. 6 (2016): 2603-2609. https://doi.org/10.1109/TED.2016.2557282.
[20] Ashita, Sajad A. Loan, Abdullah G. Alharbi, and Mohammad Rafat. "Ambipolar leakage suppression in electron–hole bilayer TFET: Investigation and analysis." Journal of Computational Electronics 17 (2018): 977-985. https://doi.org/10.1007/s10825-018-1184-y.
[21] Liu, Hu, Wenting Zhang, Zaixing Wang, Yao Li, and Huawei Zhang. "OFF-State Leakage Suppression in Vertical Electron–Hole Bilayer TFET Using Dual-Metal Left-Gate and N+-Pocket." Materials 15, no. 19 (2022): 6924. https://doi.org/10.3390/ma15196924.
[22] Anvarifard, Mohammad K., and Ali A. Orouji. "Energy band adjustment in a reliable novel charge plasma SiGe source TFET to intensify the BTBT rate." IEEE Transactions on Electron Devices 68, no. 10 (2021): 5284-5290. https://doi.org/10.1109/TED.2021.3106891
[23] Madadi, Dariush, and Ali Asghar Orouji. "Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements." The European Physical Journal Plus 136, no. 7 (2021): 785. https://doi.org/10.1140/epjp/s13360-021-01787-0
[24] Ramezani, Zeinab, and Ali A. Orouji. "A new DG nanoscale TFET based on MOSFETs by using source gate electrode: 2D simulation and an analytical potential model." Journal of the Korean Physical Society 71 (2017): 215-221. https://doi.org/10.3938/jkps.71.215
[25] Ahangari, Zahra, and Somaye Mahmodi. "Design and Sensitivity Analysis of Steep-Slope Bi-Channel Vertical Tunnel Field Effect Transistor." Silicon 13 (2021): 1917-1924. https://doi.org/10.1007/s12633-020-00579-y.
[26] ATLAS User Manual, Santa Clara, USA: Silvaco International, 2019.
[27] Kim, Jang Hyun, Sangwan Kim, and Byung-Gook Park. "Double-gate TFET with vertical channel sandwiched by lightly doped Si." IEEE Transactions on Electron Devices 66, no. 4 (2019): 1656-1661. https://doi.org/10.1109/TED.2019.2899206