Design of a Ddsm Modulator to Reduce Hardware and Power Dissipation in Fractional Frequency Synthesizers

Document Type : Research Article

Authors

Department of Electrical Engineering, Sho. C, Islamic Azad University, Shoushtar, Iran.

10.22075/mseee.2026.39635.1238

Abstract

The output of a Digital Delta-Sigma Modulator (DDSM) is always a periodic signal, and the input is constant. A hybrid DDSM is a premiere to its conventional counterpart for having a potential speed, by the choice of its smaller bus. Random techniques and deterministic methods are two strategies to maximize the periodicity. The dither signal is used in the random approach to enhance the signal cycle. The deterministic procedure causes the modulator's internal structure to alter. The majority of randomized approaches eliminate spurious tones. A novel approach for the DDSM modulator is suggested in this paper to improve the output period while reducing the undesired tones. Modulators with different word lengths are proposed in this paper. The length of the input word is divided into several parts, and each part is entered into a modulator to reduce hardware consumption. Consequently, the power consumption is decreased. Moreover, in this structure, the dither signal is used to change the alternating state of the output and reduce the spurious tones. Also, a four-stage modulator is proposed, each part of which has special characteristics. In this paper, a hybrid digital sigma-delta modulator is proposed that has lower power consumption than previous methods and reduces the number of transistors. In addition, there are fewer spurious tones in the output power spectrum of this modulator. The simulation results with 0.18 µm CMOS technology by HSPICE application show that 2530 transistors are used, which is a 15% decrease compared to the conventional method.

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References

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Journal of Modeling and Simulation in Electrical and Electronics Engineering
Volume 6, Issue 1 - Serial Number 23
In Progress
March 2026
Pages 13-19

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History

  • Receive Date: 08 November 2025
  • Revise Date: 30 November 2025
  • Accept Date: 11 January 2026

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